Clock balanced segmentation digital filter provided with optimun area of data path

ABSTRACT

The present invention generally relates to provide a clock balanced segmentation digital filter, which is provided with an optimum area of a data path. The digital filter includes a controlling unit, which is connecting with a register, a multiplexer unit, and an arithmetic and logic unit. The present invention utilizes the controlling unit to initialize the filter parameter stored in the register and to segment the whole logic operation procedure to a plurality of operation steps and to arrange the operation procedure. The multiplexer unit is connecting with the register and the arithmetic and logic unit. The multiplexer unit controlled by the controlling unit is choosing the require parameter and data to output into the arithmetic and logic unit to perform the operation. The operation result is stored in the register for using as the following operation parameter. The present is provided with advantages of scaling down the area of logic circuit, low power consumption and rapid operation.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a filter, and moreparticularly relates to a clock balanced segmentation digital filter,which is provided with a simple circuit design and a small area.

2. Description of the Prior Art

Currently, with the improvement of the digital technology and highlyapplication of the integrated circuits, using the digital technology totreatment the signal is become a commonly used method. The procedure ofthe conventional digital signal treatment includes utilizing ananalog/digital converter (A/D converter) to convert the analog signal tothe digital signal representation. Then, the digital signal is performan appropriate treatment and the obtained result is returned to ananalog output signal via the analog/digital converter (A/D converter).Hence, the key of the digital signal treatment is to use the digitalfilter selectively treating the signal.

In general, the main function of the common filter is to make thesignal, after the complex operation formula designed therein, to enhancethe amplitude of vibration or the frequency characteristic of therequired signal at a specified frequency range so as to obtain theoutput signal with a high quality and an anti-miscellaneous ability atthe specified frequency to reduce the unwanted amplitude of vibration orthe unwanted frequency characteristic. The circuit operation design ofthe prior filter, because each operation formula must require aoperation unit to perform the operation, so the filter, which isrequired complex operation, must utilize a plurality of adders,subtracters, multipliers, and operation unit to compose the requiredoperation circuit for the filter. Hence, the filter requires hardwarewith complex design and a larger area for arranging the hardware.Presently, the prior filter cannot match the microminiaturized requireof the filter. Besides, owing to each operation unit have a delay timein the operation, the prior filter used such adders, subtracters,multipliers therein will cause the require of a longer delay time of theoperation of the whole filter, so the filter can not achieve the rapidrequire of wave filtering.

Obviously, the main spirit of the present invention is to providedigital filter with a small area and rapid operation, and then somedisadvantages of well-known technology are overcome.

SUMMARY OF THE INVENTION

The primary object of the invention is to provide a digital filter,which is utilizing the technology of the sharing resource to compressthe complex operation procedure of the signal treatment of the digitalfilter so as the present invention can only require one adder-subtracterand one shifter to achieve the equal effect and provide with theadvantages of scaling down the area of logic circuit, low powerconsumption and rapid operation.

Another object of the invention is to provide a simple designed digitalfilter to properly segment the length of the logic operation toeffectively enhance the speed of the clock so as the digital filter canachieve the advantage of rapid operation.

In order to achieve previous objects, the present invention provides adigital filter. The clock balanced segmentation digital filter includesthe following elements. An arithmetic and logic unit is composing of anadder-subtracter and a shifter. A register is used for storing thefilter parameter and operation data, which are required for theoperation. A controlling unit is connecting with the register and amultiplexer unit so as the multiplexer unit controlled by thecontrolling unit is choosing the require parameter and data to outputinto the arithmetic and logic unit to perform the operation and then theoperation result is stored in the register for using as the followingoperation parameter.

Other advantages of the present invention will become apparent from thefollowing description taken in conjunction with the accompanyingdrawings wherein are set forth, by way of illustration and example,certain embodiments of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and many of the accompanying advantages of thisinvention will become more readily appreciated as the same becomesbetter understood by reference to the following detailed description,when taken in conjunction with the accompanying drawings, wherein:

FIG. 1 is a schematic representation of a block diagram of the digitalfilter, in accordance with the present invention; and

FIG. 2 is a schematic representation of the relation of lineconfiguration of the digital filter, in accordance with the presentinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to the FIG. 1 a digital filter 10 includes an infinite impulseresponse (IIR) controlling device 12 and an arithmetic and logic unit14. Wherein, the IIR controlling device 12 comprises a register 16, acontrolling unit 18 and a multiplexer unit (MUX) 20. The register 16 isconnecting with the controlling unit 18 so as to utilize the register 16storing the required filter parameter in the operation and receiving theoperation data from the controlling unit 18. In the beginning of theoperation, the filter parameter stored in the register 16 is initializedby the controlling unit 18. However, the multiplexer unit (MUX) 20 isconnected to the controlling unit 18, the register 16, and thearithmetic and logic unit 14, so the multiplexer unit (MUX) 20 isaccording to the control of the controlling unit 18 to choosing therequired filter parameter and the operation data in the operation tooutput into the arithmetic and logic unit 14. At the same time, thearithmetic and logic unit 14 would directly receive the data from thecontrolling unit 18 to match the filter parameter and to perform theoperation. The new obtained parameter from the operation is stored intothe register 16 to use for the operation parameter in the following use.

Referring to the FIG. 2, the arithmetic and logic unit 14 mentionedabove is composed of an adder-subtracter 22 and a shifter 24. Wherein,the adder-subtracter 22 is provided with three input ends and one outputend, respectively shown as a1, a2, a3, a4. The input end a1 and theinput end a2 are connected with the multiplexer unit (MUX) 20. The inputend a3 is connected with the controlling unit 18 and the output end a4is connected with the register 16. In the present invention, the inputend a1 and the input end a2 are respectively receiving two numerals,such as the filter parameter or data inputted from the multiplexer unit(MUX) 20. The input end a3 is receiving the performing signal from thecontrolling unit 18 to perform adding or subtracting to those twonumerals. After adding or subtracting those two numerals via theadder-subtracter 22, the output end a4 of the adder-subtracter 22 isoutputting a numeral (a new operation parameter) into the register 16 ofthe IIR controlling device 12 and to be stored therein. In the samereason, the shifter 24 is arranged two input ends connecting with themultiplexer unit (MUX) 20 and one output end connecting with theregister 16, respectively shown as s1, s2, s3. In the present invention,a numeral is inputted into the input end s1 and the required bit amountto shift the numeral is inputted into the input end s2 for the numeralinputted via the output end s3 after the operation of the shifter 24 andstored in the register 16 for the following operation. Besides, in thewhole IIR controlling device 12, such as shown in the FIG. 2, exceptfour circuit ends a1′, a2′, a3′, and a4′ used for the internal outputend and input end of the adder-subtracter mentioned above, and exceptthree circuit ends s1′, s2′, s3′ used for the internal output end andinput end of the shifter, there are another four circuit endsrespectively for reset input, clock input, external filtering-requireddata input, the storbe signal input, such as external input ends arerespectively shown as R, C, D1, and S1. Besides, there are another twocircuit ends, such shown as D2 and S2, are respectively used forinputting data after the treatment of the filter and outputting thestorbe signal.

The present invention utilizes the controlling unit 18 mentioned aboveto control the internal operation procedure of the whole digital filter.When the digital filter is performing the initializing step, thecontrolling unit 18 only provides few necessary parameters to store intothe register 16 and appropriately segment the length of the logicoperation. The logic operation is speared into few simple operationsteps (such as numeral adding, numeral subtracting, and numeralshifting) to help the operation of the adder-subtracter 22 and theshifter 24 and arrange the order of each operation step at the sametime. After, the multiplexer unit (MUX) 20 controlled by the controllingunit 18 is choosing two operated-required numerals from the register 16and then transferring into the arithmetic and logic unit 14 to performthe operation to produce a new parameter and then storing in theregister 16. Repeating and repeating the above steps, there are more andmore parameters stored in the register 16 until the controlling unit 18finishing the whole logic operation.

To sum up the forgoing, the present invention merely utilizes oneadder-subtracter 22 and one shifter 24 to compose of the arithmetic andlogic unit 14 repeating performing numeral operations. The presentinvention is utilizing the technology of the sharing resource tocompress the complex operation procedure of the signal treatment of thedigital filter so as the present invention only require oneadder-subtracter and one shifter to achieve the equal effect and providewith the advantages of scaling down the area of logic circuit, low powerconsumption and match the microminiaturized require of the filter.Furthermore, the present invention properly segments the length of thelogic operation to effectively enhance the speed of the clock so as thedigital filter can achieve the advantage of rapid operation.

Of course, it is to be understood that the invention described hereinneed not be limited to these disclosed embodiments. Various modificationand similar changes are still possible within the spirit of thisinvention. In this way, all such variations and modifications areincluded within the intended scope of the invention and the scope ofthis invention should be defined by the appended claims.

1. A clock balanced segmentation digital filter which is provided withan optimum area of a data path, said digital filter comprising: aregister for storing a plurality of operational parameters; a singlemultiplexer unit having a first input coupled to an output of saidregister; a single arithmetic and logic unit having an input coupled toan output of said multiplexer unit and an output coupled to saidregister for storing a current arithmetic operation result thereof insaid register as a new operational parameter; and, a controlling unitcoupled to said register and storing an initial filter parametertherein, said controlling unit being coupled to said multiplexer unitand said arithmetic and logic unit for segmenting a required operationprocedure into a plurality of sequential operation steps; wherein saidarithmetic logic unit includes a shifter and an adder-subtracter, saidshifter having one input coupled to said output of said multiplexer unitfor receiving a data signal therefrom and another input coupled to anoutput of said controlling unit for receiving a bit shift control signalfor controlling the number of bits of the data signal that are to beshifted, said shifter having an output coupled to said register forstoring said bit shifted data signal therein, said adder-subtracterhaving a pair of first inputs coupled to said multiplexer unit forreceiving data including said initial filter parameter to be combined byone of an addition or subtraction operation and a second input coupledto said controlling unit for receiving a control signal therefrom forcontrolling addition and subtraction operations thereof, saidadder-subtracter having an output coupled to said register for storingsaid current arithmetic operation result.